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(R)
Integrated Device Technology, Inc.
128K x 8 64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
DESCRIPTION:
IDT7M1001 IDT7M1003
FEATURES
* High-density 1M/512K CMOS Dual-Port Static RAM module * Fast access times: --Commercial 35, 40ns --Military 40, 50ns * Fully asynchronous read/write operation from either port * Full on-chip hardware support of semaphore signaling between ports * Surface mounted LCC (leadless chip carriers) components on a 64-pin sidebraze DIP (Dual In-line Package) * Multiple Vcc and GND pins for maximum noise immunity * Single 5V (10%) power supply * Input/outputs directly TTL-compatible
PIN CONFIGURATION(1)
VCC R/WL
OEL CSL SEML
A0L A1L GND A2L A3L A4L A5L A6L A7L A8L A9L A10L A11L A12L A13L A14L A15L A16L I/O0L I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
GND R/WR
OER CSR SEMR
A0R A1R A2R A3R A4R A5R A6R A7R A8R A9R A10R A11R A12R A13R A14R A15R A16R GND I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R I/O7R VCC
The IDT7M1001/IDT7M1003 is a 128K x 8/64K x 8 highspeed CMOS Dual-Port Static RAM module constructed on a multilayer ceramic substrate using eight IDT7006 (16K x 8) Dual-Port RAMs and two IDT FCT138 decoders or depopulated using only four IDT7006s and two decoders. This module provides two independent ports with separate control, address, and I/O pins that permit independent and asynchronous access for reads or writes to any location in memory. System performance is enhanced by facilitating port-to-port communication via semaphore (SEM) "handshake" signaling. The IDT7M1001/1003 module is designed to be used as stand-alone Dual-Port RAM where on-chip hardware port arbitration is not needed. It is the users responsibility to ensure data integrity when simultaneously accessing the same memory location from both ports. The IDT7M1001/1003 module is packaged on a multilayer co-fired ceramic 64-pin DIP (Dual In-line Package) with dimensions of only 3.2" x 0.62" x 0.38". Maximum access times as fast as 35ns over the commercial temperature range are available. All inputs and outputs of the IDT7M1001/1003 are TTLcompatible and operate from a single 5V supply. Fully asynchronous circuitry is used, requiring no clocks or refreshing for operation of the module. All IDT military module semiconductor components are manufacured in compliance with the latest revision of MILSTD-883, Class B, making them ideally suited to applications demanding the highest level of performance and reliability.
PIN NAMES
Left Port A (0-16)L I/O (0-7)L R/WL
CSL OEL SEML
Right Port A (0-16)R I/O (0-7)R R/WR
CSR OER SEMR
Description Address Inputs Data Inputs/Outputs Read/Write Enables Chip Select Output Enable Semaphore Control Power Ground
2804 tbl 01
VCC GND
2804 drw 01
DIP TOP VIEW
NOTE: 1. For the IDT7M1003 (64K x 8) version, Pins 23 and 43 must be connected to GND for proper operation of the module.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
(c)1995 Integrated Device Technology, Inc.
MARCH 1995
DSC-7066/5
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IDT7M1001/1003 128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM 7M1001
CS L L_A16 L_A15 L_A14
CS R
CS L
CS R
CS L
L_CS
74FCT138 74FCT138 R_CS
L_A0-13 L_OE L_R/W
L_I/O0-7
CS L
CS R
CS L
CS R
CS L
7006
7006
7006
L_SEM
7M1003
L_A15 L_A14
L_CS
74FCT138 74FCT138 R_CS
L_A0-13 L_OE L_R/W
L_I/O0-7
CS L
CS R
CS L
R CS
CS L
7006
7006
7006
L_SEM
7.5
7025 CS R CS R
CS R
7006
7006
7006
7006 R_I/O0-7 CS L CS R
R_R/W R_OE R_A0-13
R_A14 R_A15 R_A16 CS L 7006 CS R
R_SEM
2804 drw 02
R_I/O0-7
R_R/W R_OE R_A0-13
R_A14 R_A15 CS L 7006 CS R
R_SEM
2804 drw 03
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IDT7M1001/1003 128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM Rating Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Commercial -0.5 to +7.0 Military -0.5 to +7.0 Unit V
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Grade Military Ambient Temperature -55C to +125C 0C to +70C GND 0V 0V VCC 5.0V 10% 5.0V 10%
2804 tbl 04
TA TBIAS TSTG IOUT
0 to +70 -55 to +125 -55 to +125 50
-55 to +125 -65 to +135 -65 to +150 50
C C C mA
Commercial
NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2804 tbl 02
RECOMMENDED DC OPERATING CONDITIONS
Symbol VCC GND VIH VIL Parameter Supply Voltage Supply Voltage Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0.5
(1)b
Typ. 5.0 0 b -
Max. 5.5 0 6.0 0.8
Unit V V V V
2804 tbl 05
CAPACITANCE(1) (TA = +25C, f = 1.0MHz)
Symbol CIN1 CIN2 Parameter Input Capacitance
(CS or
SEM)
Test Conditions VIN = 0V VIN = 0V
Max. 15 100
Unit pF pF
NOTE: 1. VIL (min.) = -3.0V for pulse width less than 20ns.
Input Capacitance
(Data, Address, All Other Controls)
COUT
Output Capacitance
(Data)
VOUT = 0V
100
pF
2804 tbl 03
NOTE: 1. This parameter is guaranteed by design but not tested.
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V 10%, TA = -55C to +125C or 0C to +70C) Commercial Symbol ICC2 ICC1 ISB1 Parameter Dynamic Operating Current (Both Ports Active) Standby Supply Current (One Port Active) Standby Supply Current (TTL Levels) Full Standby Supply Current (CMOS Levels) Test Conditions VCC = Max., CS VIL, SEM VIH Outputs Open, f = fMAX VCC = Max., L_CS or R_CS VIH Outputs Open, f = fMAX VCC = Max., L_CS and R_CS VIH Outputs Open, f = fMAX L_SEM and R_SEM VCC -0.2V ISB2 L_CS and R_CS VCC -0.2V VIN > VCC 0.2V or < 0.2V L_SEM and R_SEM VCC -0.2V -- 125 65 -- 245 125 mA Min. Max. -- -- --
(1)
Military
(2)
Max.
Min. Max.(1) Max.(2) Unit -- -- -- 1130 905 685 790 565 345 mA mA mA
940 750 565
660 470 285
NOTES: 1. IDT7M1001 (128K x 8) version only. 2. IDT7M1003 (64K x 8) version only.
2804 tbl 06
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IDT7M1001/1003 128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS
(VCC=5.0V 10%, TA = -55C to +125C and 0C to +70C)
Symbol |ILI| |ILI| |ILO| VOL VOH Parameter Input Leakage (Address, Data & Other Controls) Input Leakage (CS and SEM) Output Leakage (Data) Output Low Voltage Output High Voltage Test Conditions VCC = Max. VIN = GND to VCC VCC = Max. VIN = GND to VCC
CS
IDT7M1001 Min. Max. -- -- -- -- 2.4 80 10 80 0.4 --
IDT7M1003 Min. Max. -- -- -- -- 2.4 40 10 40 0.4 --
Unit A A A V V
2804 tbl 07
VCC = Max. VIH, VOUT = GND to VCC IOL = 4mA IOH = -4mA
VCC = Min. VCC = Min.
AC TEST CONDITIONS
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels Output Load GND to 3.0V 5ns 1.5V 1.5V See Figures 1 and 2
2804 tbl 08
+5 V
+5 V
480 DATAOUT 255 30 pF* DATAOUT 255
480
5 pF*
2804 drw 04
2804 drw 05
Figure 1. Output Load
Figure 2. Output Load (for tCLZ, tCHZ, tOLZ. tOHZ, tWHZ, tOW) *Including scope and jig.
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IDT7M1001/1003 128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V 10%, TA = -55C to +125C and 0C to +70C)
-35 -40 -50
Symbol
Read Cycle tRC tAA tACS(2) tOE tOH tCLZ
(1) (1)
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time Address Access Time Chip Select Access Time Output Enable Access Time Output Hold From Address Change Chip Select to Output in Low-Z Chip Deselect to Output in High-Z Output Enable to Output in Low-Z Output Disable to Output in High-Z Chip Select to Power-Up Time Chip Disable to Power-Down Time
SEM
35 -- -- -- 3 3 -- 3 -- 0 -- 15
-- 35 35 20 -- -- 20 -- 20 -- 50 --
40 -- -- -- 3 3 -- 3 -- 0 -- 15
-- 40 40 25 -- -- 20 -- 20 -- 50 --
50 -- -- -- 3 3 -- 3 -- 0 -- 15
-- 50 50 30 -- -- 25 -- 25 -- 50 --
ns ns ns ns ns ns ns ns ns ns ns ns
tCHZ tOLZ
(1) (1)
tOHZ tPU tPD
(1) (1)
tSOP
Flag Update Pulse (OE or SEM)
Write Cycle tWC tCW tAW tAS1 tAS2 tWP tWR tDW tDH(4) tOHZ(1) tWHZ(1) tOW(1, 4) tSWRD tSPS
(4) (3) (2)
Write Cycle Time Chip Select to End-of-Write Address Valid to End-of-Write Address Set-up to Write Pulse Time Address Set-up to CS Time Write Pulse Width Write Recovery Time Data Valid to End-of-Write Data Hold Time Output Disable to Output in High-Z Write Enable to Output in High-Z Output Active from End-of-Write
SEM SEM
35 30 30 5 0 30 0 25 0 -- -- 0 15 15
-- -- -- -- -- -- -- -- -- 20 20 -- -- --
40 35 35 5 0 35 0 30 0 -- -- 0 15 15
-- -- -- -- -- -- -- -- -- 20 20 -- -- --
50 40 40 5 0 40 0 35 0 -- -- 0 15 15
-- -- -- -- -- -- -- -- -- 25 25 -- -- --
ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Flag Write to Read Time Flag Contention Window
Port-to-Port Delay Timing tWDD(5) tDDD
(5)
Write Pulse to Data Delay Write Data Valid to Read Data Valid
-- --
60 45
-- --
65 50
-- --
70 55
ns ns
2804 tbl 09
NOTES: 1. This parameter is guaranteed by design but not tested. 2. To access RAM CS VIL and SEM VIH. To access semaphore, CS VIH and SEM VIL. 3. tAS1= 0 if R/W is asserted LOW simultaneously with or after the CS LOW transition. 4. For CS controlled write cycles, tWR= 5ns, tDH= 5ns, tOW= 5ns. 5. Port-to-Port delay through the RAM cells from the writing port to the reading port.
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IDT7M1001/1003 128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1 (EITHER SIDE)(1,2,4)
t RC ADDRESS t AA t OH t OH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
2804 drw 06
TIMING WAVEFORM OF READ CYCLE NO. 2 (EITHER SIDE)(1,3,5)
t ACS
CS
t CHZ t OE
(6)
OE
t OLZ (6) DATA OUT tCLZ t PU ICC CURRENT ISB 50%
(6) (6)
t OHZ
(6)
DATA VALID
t PD
(6)
50%
NOTES: 1. R/W is HIGH for Read Cycles 2. Device is continuously enabled. CS = LOW. This waveform cannot be used for semaphore reads. 3. Addresses valid prior to or coincident with CS transition LOW. 4. OE = LOW. 5. To access RAM, CS = LOW, SEM = H. To access semaphore, CS = HIGH and SEM = LOW. 6. This parameter is guaranteed by design but not tested.
2804 drw 07
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IDT7M1001/1003 128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (R/W CONTROLLED TIMING)(1,3,5,8) W
t ADDRESS t OHZ (9)
OE
WC
CS
t AW
t AS (6) R/W
t WP(2)
t WR (7)
t WHZ (9) DATA OUT
(4)
t OW (9)
(4)
t DW DATA
IN
t DH DATA VALID
2804 drw 08 NOTES: 1. R/W is HIGH for Read Cycles 2. Device is continuously enabled. CS = LOW. UB or LB = LOW. This waveform cannot be used for semaphore reads. 3. Addresses valid prior to or coincident with CS transition low. 4. OE = LOW. 5. To access RAM, CS = LOW, UB or LB = LOW, SEM = H. To access semaphore, CS = HIGH and SEM = LOW. 6. Timing depends on which enable signal is asserted last. 7. Timing depends on which enable signal is de-asserted first. 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse width be as short as the specified tWP. 9. This parameter is guaranteed by design but not tested.
TIMING WAVEFORM OF WRITE CYCLE NO. 2 ( CS CONTROLLED TIMING)(1,3,5,8)
t ADDRESS
CS
WC
t AW t AS (6)
UB or LB
t WP (2)
t WR (7)
R/W t DW DATA
IN
t DH DATA VALID
2804 drw 09 NOTES: 1. R/W must be HIGH during all address transitions. 2. A write occurs during the overlap (tWP) of a LOW UB or LB and a LOW CS and a LOW R/W for memory array writing cycle. 3. tWR is measured from the earlier of CS or R/W (or SEM or R/W) going HIGH to the end of write cycle. 4. During this period, the I/O pins are in the output state and input signals must not be applied. 5. If the CS or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. 6. Timing depends on which enable signal is asserted last. 7. Timing depends on which enable signal is de-asserted first. 8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP. 9. This parameter is guaranteed by design but not tested.
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IDT7M1001/1003 128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING (EITHER SIDE)(1)
t AA A 0 - A2 VALID ADDRESS t AW
SEM
t OH
VALID ADDRESS t
ACS
t WR t WP t SOP t DW
DATA 0 t AS R/W
DATA IN VALID t WP t DH
DATAOUT VALID
t OE t SWRD
OE
t SOP WRITE CYCLE READ CYCLE
2804 drw 10
NOTE: 1. CS = HIGH for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE CONTENTION(1,3,4)
A 0A - A 2A MATCH
SIDE
(2)
"A"
R/W A
SEM A A 0B - A 2B
t SPS MATCH
SIDE
(2)
"B"
R/W B
SEM B
2804 drw 11
NOTES: 1. D0R = D0L = LOW, L_CS = R_CS = HIGH. Semaphore Flag is released form both sides (reads as ones from both sides) at cycle start. 2. "A" may be either left or right port. "B" is the opposite port from "A". 3. This parameter is measured from R/WA or SEMA going HIGH to R/WB or SEMB going HIGH. 4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
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IDT7M1001/1003 128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT DELAY(1)
t WC ADDR
R
MATCH t WP
R/W
R
t DW DATA IN
R
t DH
VALID
ADDR L
MATCH
t WDD DATA
OUT L
VALID t DDD
NOTE: 1. L_CS = R_CS = LOW.
WRITE CYCLE LEFT PORT
READ CYCLE RIGHT PORT
2804 drw 12
TRUTH TABLES TABLE I: NON-CONTENTION READ/WRITE CONTROL(1)
Inputs(1)
CS
Outputs
SEM
R/W W X L H X
OE
I/O0 - I/O7 High-Z DATAIN DATAOUT High-Z
Mode Deselected: Power Down Write to Both Bytes Read Both Bytes Outputs Disabled
2804 tbl 10
H L L X
X X L H
H H H X
NOTE: 1. AOL -- A12 A0R -- A12R
TABLE II: SEMAPHORE READ/WRITE CONTROL(1)
Inputs
CS
Outputs
SEM
R/W W H X
OE
I/O0 - I/O7 DATAOUT DATAIN --
Mode Read Data in Semaphore Flag Write DIN0 into Semaphore Flag Not Allowed
2804 tbl 11
H X L
L X X
L L L
NOTE: 1. AOL -- A12 A0R -- A12R
SEMAPHORE OPERATION
For more details regarding semaphores & semaphore operations, please consult the IDT7006 datasheet.
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IDT7M1001/1003 128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PACKAGE DIMENSIONS 7M1001
3.190 3.210 0.615 0.635
0.605 0.625 PIN1 0.010 0.050
TOP VIEW
0.330 MAX.
0.380 MAX.
0.007 0.013
SIDE VIEW
0.035 0.060
0.015 0.022
0.100 TYP.
0.125 0.175
SIDE VIEW
BOTTOM VIEW
2804 drw 13
7M1003
3.190 3.210 0.605 0.625 0.615 0.635
PIN1 0.010 0.070
TOP VIEW
0.310 MAX.
0.380 MAX.
0.007 0.013
SIDE VIEW
0.035 0.060
0.015 0.022
0.100 TYP.
0.125 0.175
SIDE VIEW
BOTTOM VIEW
2804 drw 14
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IDT7M1001/1003 128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDT XXXX Device type A Power 999 Speed A Package A Process/ Temperature range BLANK Commercial (0C to +70C) B Military (-55C to +125C) Semiconductor components compliant to MIL-STD-883, Class B C 35 40 50 S Sidebraze DIP (Dual In-line Package) (Commercial Only) Nanoseconds (Military Only) Standard Power
7M1001 128K x 8 Dual-Port Static RAM Module 7M1003 64K x 8 Dual-Port Static RAM Module
2804 drw 15
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